1. Field of the Invention
The present invention relates to signal level adjusting circuits. More particularly, the present invention relates to signal level adjusting circuits for reducing the influence on connected amplifying stages that have connecting portions with different DC voltages, i.e. when the DC voltage at an output terminal of the first amplifying stage and the DC voltage at an input terminal of the second amplifying stage are different. The reduction is achieved by connecting a coupling stage having at least one series resistor between the output terminal of the first amplifying stage and the input terminal of the second amplifying stage.
2. Description of the Related Art
Generally, cellular telephones contain circuitry including a bipolar integrated circuit (IC) and a complementary metal oxide semiconductor (CMOS) IC. The bipolar IC includes an automatic gain control (AGC) amplifier, a quadrature phase-shift keying (QPSK) demodulator, and a buffer amplifier, while the CMOS IC includes an input amplifier, a low-pass filter, and an analog-to-digital (A/D) converter. An output terminal of the buffer amplifier in the bipolar IC and an input terminal of the input amplifier in the CMOS IC are coupled.
FIG. 2 is a block diagram illustrating critical portions of the cellular telephone described above. Referring to FIG. 2, the cellular telephone includes a radio frequency (RF) signal input terminal 20, a radio frequency amplifier (RF AMP) 21, a frequency mixer (MIX) 22, a local oscillator (LO OSC) 23, a buffer amplifier 24, a bipolar IC 25, a CMOS IC 26, a mobile station model (MSM) 27, and a signal output terminal 28. The bipolar IC 25 includes an automatic gain control amplifier (AGC AMP) 29, a QPSK demodulator 30, an output buffer amplifier 31, a signal input terminal 32, and two signal output terminals 331 and 332. The CMOS IC 26 includes an input amplifier 34, a low-pass filter (LF) 35, an analog-to-digital converter (A/D) 36, two signal input terminals 371 and 372, and a signal output terminal 38.
The RF AMP 21 has an input terminal connected with the RF signal input terminal 20 and an output terminal connected with a first input terminal of the MIX 22. The MIX 22 has a second input terminal connected with an output terminal of the buffer amplifier 24 and an output terminal connected with the signal input terminal 32. The LO OSC 23 has an output terminal connected with an input terminal of the buffer amplifier 24. The AGC AMP 29 has an input terminal connected with the signal input terminal 32 and an output terminal connected with an input terminal of the QPSK demodulator 30. The output buffer amplifier 31 has two input terminals connected with two output terminals, respectively, of the QPSK demodulator 30, and two output terminals connected with the signal output terminals 331 and 332, respectively. The input amplifier 34 has two input terminals connected with the signal input terminals 371 and 372, respectively, and an output terminal connected with an input terminal of the LF 35. The A/D 36 has an input terminal connected with an output terminal of the LF 35 and an output terminal connected with the signal output terminal 38. The MSM 27 has an input terminal connected with the signal output terminal 38 and an output terminal connected with the signal output terminal 28. Connecting lines (no reference numeral) interconnect the signal output terminals 331 and 332 and the signal input terminals 371 and 372, respectively.
A cellular telephone having the above construction operates as follows: when a received RF signal is applied to the RF signal input terminal 20, the RF signal is amplified by the RF AMP 21 and is subsequently supplied to the MIX 22. Simultaneously, a local oscillation signal generated by the LO OSC 23 is supplied to the MIX 22 via the buffer amplifier 24. The MIX 22 mixes the RF signal and the local oscillation signal and outputs an intermediate frequency (IF) signal of the difference frequency to the bipolar IC 25. The IF signal supplied to the bipolar IC 25 is amplified by the AGC AMP 29, and the amplified IF signal is demodulated by the QPSK demodulator 30 to form a demodulation signal. The demodulation signal is amplified by the output buffer amplifier 31 and is output from the bipolar IC 25 to the subsequent CMOS IC 26. The input amplifier 34 amplifies the demodulation signal supplied to the CMOS IC 26 and subsequently, unwanted frequency components are removed from the amplified signal by the LF 35. The demodulation signal then undergoes analog-to-digital conversion by the A/D 36 to form a digital signal. The digital signal is supplied to the signal output terminal 38. The digital signal is converted into an available signal by the MSM 27, and is supplied from the signal output terminal 38 to an external circuit (not shown).
FIG. 3 is a circuit diagram of a detailed construction of the coupling portion between the output buffer amplifier 31 of the bipolar IC 25 and the input amplifier 34 of the CMOS IC 26. Referring to FIG. 3, the output buffer amplifier 31 includes a first bipolar transistor 311, a second bipolar transistor 312, a first current supply 313 connected between an emitter of the first bipolar transistor 311 and ground, and a second current supply 314 connected between an emitter of the second bipolar transistor 312 and ground. The first bipolar transistor 3131 and the second bipolar transistor 312 form a balanced amplifying circuit. The signal output terminals 33, and 332 of the bipolar IC 25 are connected with the emitters of the first bipolar transistor 311 and the second bipolar transistor 312, respectively. The input amplifier 34 includes a first MOS field effect transistor (MOSFET) 341 and a second MOSFET 342. The first MOSFET 341 and the second MOSFET 342 form a balanced amplifying circuit. The signal input terminals 371 and 372 of the CMOS IC 26 are connected with gates of the first MOSFET 341 and the second MOSFET 342, respectively. The same reference numerals are given to the same components as those shown in FIG. 2.
The operation of the coupling portion between the output buffer amplifier 31 and the input amplifier 34 is described below. When a balanced demodulation signal is supplied to bases of the first bipolar transistor 311 and the second bipolar transistor 312, the emitter-follower-connected first and second bipolar transistors 311 and 312 amplify the demodulation signal. The amplified balanced demodulation signal is supplied from the emitters of the first and second bipolar transistors 311 and 312 to the signal output terminals 331 and 332, respectively. Subsequently, the balanced demodulation signal is transmitted from the signal output terminals 331 and 332 through the connecting lines to the signal input terminals 371 and 372, respectively. The balanced demodulation signal at the signal input terminals 371 and 372 is supplied to gates of the source-grounded first and second MOSFETs 341 and 342, respectively, which form a balanced amplifying circuit. The first MOSFET 341 and the second MOSFET 342 amplify the balanced demodulation signal.
The coupling portion between the output buffer amplifier 31 and the input amplifier 34 in the cellular telephone is arranged such that the output buffer amplifier 31 is a part of the bipolar IC 25 and the input amplifier 34 is a part of the CMOS IC 26. In this case, the supply voltage driving the bipolar IC 25 may be different from the supply voltage driving the CMOS IC 26. This may cause a difference between a DC voltage V1 obtained at the signal output terminals 331 and 332 of the bipolar IC 25 and a DC voltage V2 obtained at the signal input terminals 371 and 372 of the CMOS IC 26. When connecting lines interconnect the signal output terminals 331 and 332 and the signal input terminals 371 and 372 having different DC voltages, an electrical current flows through the connecting lines from the higher DC voltage ends (e.g., the signal input terminals 371 and 372) to the lower DC voltage ends (e.g., the signal output terminals 331 and 332). As a result, operating points of the first bipolar transistor 311, the second bipolar transistor 312, the first MOSFET 341, and the second MOSFET 342 are shifted.
An example of the DC voltage V1 obtained at the signal output terminals 331 and 332 and the DC voltage V2 obtained at the signal input terminals 371 and 372 is described below. If the first and second bipolar transistors 311 and 312 each have an emitter current value of 0.8 mA and the first and second current supplies 313 and 314 each have a current value of 0.8 mA, the DC voltage V1 obtained at the signal output terminals 33, and 332 is approximately 1.0 V. In contrast, the DC voltage V2 obtained at the signal input terminals 371 and 372 is normally about 1.7 V. Hence, there is a difference of approximately 0.7 V between the two DC voltages V1 and V2. When the signal output terminals 331 and 332 and the signal input terminals 371 and 372 are respectively connected by the connecting lines, an electrical current flows through the connecting lines from the signal input terminals 371 and 372 to the signal output terminals 331 and 332, respectively. As a result, the current values of the first current supply 313 and the second current supply 314 are substantially increased from the original value of approximately 0.8 mA, and the DC voltage V2 at the signal input terminals 371 and 372 is decreased depending on the current flowing into the connecting lines. This causes variations in the operating points of the first bipolar transistor 311, the second bipolar transistor 312, the first MOSFET 341, and the second MOSFET 342.
Accordingly, an object of the present invention is to provide a signal level adjusting circuit having a coupling stage in which there is no variation between operating points of a first amplifying stage, in a previous stage, and a second amplifying stage, in a subsequent stage, when the first and second amplifying stages are interconnected by the coupling stage.
To this end, according to the present invention, a signal level adjusting circuit is provided. The signal level adjusting circuit includes a first amplifying stage having a low output impedance, in which an output electrode of an output stage transistor is connected both to an output terminal and to ground through a current supply. The output terminal has a DC voltage with a first voltage value. The signal level adjusting circuit also includes a second amplifying stage having a high input impedance, in which a control electrode of an input stage transistor is connected with an input terminal, and a DC voltage at the input terminal has a second voltage value differing from the first voltage value, and a coupling stage including at least one series resistor, which is connected between the output terminal and the input terminal.
The first amplifying stage comprises a bipolar IC and the second amplifying stage comprises a CMOS IC. The series resistor may be selected such that, when the coupling stage is connected between the output terminal and the input terminal, a current flowing through the series resistor in the coupling stage is not greater than 10% of a current flowing through the current supply prior to connection of the coupling stage.
The coupling stage including at least one series resistor may be connected between the output terminal, connected with the output electrode of the output stage transistor, and the input terminal, connected with the control (input) electrode of the input stage transistor. The series resistor absorbs the voltage difference between a first DC voltage applied to the output terminal and a second DC voltage applied to the input terminal. Since the coupling stage is connected no variation occurs between operating points of the output stage transistor and the input stage transistor.